The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to a silicon interposer with optical connections.
There is a growing desire for xe2x80x9csystem on a chipxe2x80x9d as integrated circuit technology makes steady progress and revolutionizes our daily life. Ideally, we would like to build a computing system by fabricating all the necessary integrated circuits on one wafer, as compared with today""s method of fabricating many chips of different functions and packaging them to assemble a system. The concept of xe2x80x9csystem on a chipxe2x80x9d has been around for a long time, but in practice, it is very difficult with today""s technology to implement such a truly high-performance system because of vastly different fabrication processes and different manufacturing yields for the logic and memory circuits. To overcome some of these problems, Intel demonstrated a high-performance microprocessor and cache core based on a silicon-on-silicon multichip module technology. This technology was designed to have low interconnect parasitics and low cost. A 40 to 50% clock rate improvement was realized over a conventional packaging approach. More recently, a xe2x80x9csystem modulexe2x80x9d has recently been introduced. The module consists of two chips (logic and memory) with Chip A stacked on Chip B in a structure called Chip-on-Chip (COC) using a micro bump bonding technology (MBB). For high-performance computing systems, it is highly desirable for the microprocessor and memory devices to be located with close proximate for faster communication (high bandwidth). This leads to the consideration of very large chips and attendant lower wafer yield and productivity. However, even the largest chips which can be economically produced in any lithographic generation can contain only a relatively very small system. Therefore, in the foreseeable future, rather than building a truly integrated chip, the present trend of packaging several chips on a module will continue, but with the level of integration, on a given chip, being in part determined by the packaging capabilities. It will also be desirable to package chips in closer proximity to achieve higher performance. Another important objective is too reduce the energy required per switching event in driving circuits on the module.
The above mentioned problems with integrated circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification. An electronic packaging assembly which accords these benefits is provided.
In particular, an improved electronic packaging assembly is provided for increasing the operational bandwidth between different circuit devices, e.g. logic and memory chips, without requiring changes in current CMOS processing techniques. The electronic packaging assembly includes the use of a silicon interposer. The silicon interposer can consist of rejected wafers recycled from front-end semiconductor processing. This provides the added advantage of low cost and availability. A silicon interposer is thermally matched to the circuit devices such that coefficient of expansion mismatches are nonexistent. And, deposition of conductors on the silicon interposer""s surface is readily accomplished using a standard integrated circuit multi-layer metallurgy.
The electronic packaging assembly also includes at least one, or a number of, semiconductor chips located on opposing surfaces of the silicon interposer. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various integrated circuit devices located on the opposing surfaces of the silicon interposer. An optical detector and an optical emitter are located on the silicon interposer and couple the silicon interposer to a fiber optical network. Improved performance in the form of higher bandwidth and a lower required energy per switching event is provided by this novel electronic packaging assembly.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.